This is an invention in two-dimensional orthogonal transform for signal processing.
Of various digital signal processing methods for information compression a transform coding technique has been considered important. For example, a system capable of performing the transform-coding of image information comprises the following components: a blocking unit for dividing a target picture into blocks each made up of n.times.n picture elements; an orthogonal transform processor for performing the two-dimensional orthogonal transform of each block; a quantizer for quantizing a result found by the orthogonal transform processor (i.e., a set of transform coefficients); and an encoder for performing the variable-length encoding of the quantized transform coefficients. The orthogonal transform includes the Hadamard transform, the slant transform, and the discrete cosine transform, abbreviated DCT. The coding standards for digital storage media request that two-dimensional DCT should be continuously performed, one block at a time, at high speed. A group of plural blocks is called a macro block, and a transform coding apparatus employing a pipeline architecture by macro block has been proposed.
U.S. Pat. No. 4,791,598 discloses a two-dimensional DCT processor having a pair of one-dimensional DCT processors and a transposition memory connected between these one-dimensional DCT processors. Japanese Patent Application, published under No. 3-214256; discloses a two-dimensional DCT processor identical in the above-mentioned internal configuration with the U.S. Pat. No. 4,791,598's processor. Both of these two-dimensional DCT processors are large in size because of the two one-dimensional DCT processors. This produces the problem that integrated processors require large chip area.